Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lynxpoint: Set PCIe L1 substate capabilities register ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46134/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46134/2//COMMIT_MSG@11 PS2, Line 11: Test: build/boot google/beltino variants … and checked with lspci?
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... PS2, Line 681: /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ Would be better to put the comment into the first branch? (But it’d be inconsistent with Broadwell then.)