[coreboot-gerrit] Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related

[Jianjun Wang (Code Review)]

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu.
Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 )

Change subject: libpayload/pci: Split PCI interfaces as common and chip related
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Patch Set 39:

(1 comment)

File payloads/libpayload/drivers/pci_map_bus_ops.c:

https://review.coreboot.org/c/coreboot/+/56789/comment/fbf0868c_ceb3ae19 
PS35, Line 38: |
> Is the address always aligned? I mean, should we write "+" here?

The cfg_base should be 4K alignment, and the range of reg should be 0 ~ 4K for each device's config space.
But it makes me wondering if we should remain the capability that some device may need 4Byte alignment access.
For Mediatek chips, we will connect this address space (cfg_base) to AHB/AXI bus, so it's ok to access without 4Byte alignment.
But if some device is connected to APB bus, it's only support 32bit access, so we should guarantee alignment and calculate the correct data here, just like the 'pci_generic_config_read32/write32' functions in Linux:
https://elixir.bootlin.com/linux/latest/source/drivers/pci/access.c#L120