[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Lock down PCI BUSx:07.7 registers

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47447 )

Change subject: soc/intel/xeon_sp: Lock down PCI BUSx:07.7 registers
......................................................................

soc/intel/xeon_sp: Lock down PCI BUSx:07.7 registers

This is required for CbNT.

Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 37 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47447/1

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 8e42680..39ee8b4 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -132,4 +132,7 @@
 #define PC10_IOAPIC_ID                  0x13
 #define PC11_IOAPIC_ID                  0x14

+// D7F7 registers
+#define IIO_DFX_LCK_CTL		0x504
+
 #endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index a8cd617..8455378 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -176,4 +176,7 @@
 #define PC10_IOAPIC_ID                  0x13
 #define PC11_IOAPIC_ID                  0x14

+// D7F7 registers
+#define IIO_DFX_LCK_CTL		0x504
+
 #endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index a5b95b1..b01301c 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -355,3 +355,34 @@
    .vendor   = PCI_VENDOR_ID_INTEL,
    .device  = MMAP_VTD_STACK_CFG_REG_DEVID,
 };
+
+static void d7_f7_init(struct device *dev)
+{
+	uint16_t reg16;
+	pci_or_config16(dev, IIO_DFX_LCK_CTL, 0x3ff);
+	reg16 = pci_read_config16(dev, 0x30c);
+	reg16 &= ~(1 << 4); // allow ib mmio cfg
+	reg16 &= ~(1 << 5); // ignore acs p2p ma lpbk
+	reg16 |= (1 << 3); // me disable
+	pci_write_config16(dev, 0x30c, reg16);
+}
+
+static const unsigned short d7_f7_ids[] = {
+	0x202d,
+	0x203d,
+	0
+};
+
+static struct device_operations d7_f7_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= d7_f7_init,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver d7_f7_driver __pci_driver = {
+	.ops		= &d7_f7_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.devices	= d7_f7_ids,
+};