[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Jamie Ryu, Maulik V Vaghela, Selma Bensaid, Sridhar Siricilla, Bernardo Perez Priego, Ronak Kanabar, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54334 )

Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn
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Patch Set 8:

(2 comments)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/54334/comment/dd0087aa_e6e1fa95 
PS8, Line 52: 	/* Specifies which Type-C Ports are enabled on the system */
            : 	bool UsbTcPortEn[MAX_TYPE_C_POR
I don't think we need more options here, there are 4 devices in the devicetree for alderlake that represent these, you can use the `enabled` state of these devices to add the bits into the UPD below

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/54334/comment/5d813cdc_854b4e76 
PS8, Line 113: 	for (i = 0; i < MAX_TYPE_C_PORTS; i++)
             : 		params->UsbTcPortEn |= config->UsbTcPortEn[i] << i;
along with the above comment, I think this could look like (untested):
```
for (i = 0; i < MAX_TYPE_C_PORTS; i++) {
    /* TCSS xHCI --> Root Hub --> Type-C Port */
    const struct device_path port_path[] = {
        {.type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_TCSS_XHCI},
        {.type = DEVICE_PATH_USB, .usb.port_type = 0, .usb.port_id = 0},
        {.type = DEVICE_PATH_USB, .usb.port_type = 3, .usb.port_id = i}};
    const struct device *port = find_dev_nested_path(pci_root_bus(), port_path,
                                                                ARRAY_SIZE(port_path));
    if (is_dev_enabled(port)) {
         params->UsbTcPortEn |= BIT(i);
    }
```