Marshall Dawson has uploaded a new patch set (#10) to the change originally created by Kyösti Mälkki. ( https://review.coreboot.org/c/coreboot/+/35035 )
Change subject: arch/x86: Implement RESET_VECTOR_IN_RAM for bootblock ......................................................................
arch/x86: Implement RESET_VECTOR_IN_RAM for bootblock
Add support for devices with the reset vector pointing into DRAM. This is a specific implementation that assumes a paradigm of AMD Family 17h (a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's state appears to software like other designs, and then the actual physical addressing becomes recognizable.
Due the nature of a system where the DRAM is alive before the x86, a number of design options were considered, including the first stage as ramstage. Beginning with ramstage was infeasible because the processor must still go through the typical initial steps and be put into flat protected mode.
This patch is phase 1 of adding support and it builds a traditional bootblock image. Although running from DRAM, the unused bootblock is kept in cbfs. The details for placing the bootblock into memory are left to the soc implementation.
Sample build using amd/mandolin (currently WIP): Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 21300 none fallback/ramstage 0x5440 stage 76115 none config 0x17e00 raw 398 none revision 0x18000 raw 674 none payload_config 0x18300 raw 1593 none payload_revision 0x18980 raw 262 none (empty) 0x18b00 null 664 none fspm.bin 0x18dc0 fsp 786432 none (empty) 0xd8e00 null 3992 none fsps.bin 0xd9dc0 fsp 262144 none pci1002,15d8.rom 0x119e00 optionrom 54272 none fallback/dsdt.aml 0x127280 raw 8365 none fallback/payload 0x129380 simple elf 68099 none (empty) 0x139dc0 null 2383832 none bootblock 0x37fdc0 bootblock 524288 none
readelf of build/cbfs/fallback/bootblock.elf: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 02000000 000060 005318 00 AX 0 0 32 [ 2] .rel.text REL 00000000 006f34 0010d8 08 I 5 1 4 [ 3] .earlyram.data NOBITS 0802d000 000000 045ed8 00 WA 0 0 32 [ 4] .gnu_debuglink PROGBITS 00000000 005378 000014 00 0 0 4 [ 5] .symtab SYMTAB 00000000 00538c 000e50 10 6 61 4 [ 6] .strtab STRTAB 00000000 0061dc 000d57 00 0 0 1 [ 7] .shstrtab STRTAB 00000000 00800c 000043 00 0 0 1
91: 0802d000 0 NOTYPE GLOBAL DEFAULT 3 _earlyram_stack 68: 0802d800 0 NOTYPE GLOBAL DEFAULT 3 _eearlyram_stack 175: 0802d800 0 NOTYPE GLOBAL DEFAULT 3 _preram_cbmem_console 199: 0802ee00 0 NOTYPE GLOBAL DEFAULT 3 _epreram_cbmem_console 120: 0802ee00 0 NOTYPE GLOBAL DEFAULT 3 _timestamp 221: 0802f000 0 NOTYPE GLOBAL DEFAULT 3 _etimestamp 153: 0802f000 0 NOTYPE GLOBAL DEFAULT 3 _bss 130: 08072ed8 0 NOTYPE GLOBAL DEFAULT 3 _ebss
Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M Makefile.inc M src/arch/x86/Kconfig M src/arch/x86/assembly_entry.S A src/arch/x86/early_ram.ld M src/arch/x86/memlayout.ld M src/cpu/Kconfig M src/include/memlayout.h 7 files changed, 79 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35035/10