[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/common/block/pci: Ignore disabled bridges

[Maximilian Brune (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph.

Maximilian Brune has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86216?usp=email )

Change subject: soc/amd/common/block/pci: Ignore disabled bridges
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Patch Set 1:

(1 comment)

File src/soc/amd/common/block/pci/pcie_gpp.c:

https://review.coreboot.org/c/coreboot/+/86216/comment/e7137ceb_41e54111?usp... :
PS1, Line 58: static void pcie_internal_gpp_enable(struct device *dev)
            : {
            : 	assert(dev->enabled);
            : 	if (!dev->enabled) {
            : 		/*
            : 		 * Cannot hide PPB devices! Must keep them enabled to
            : 		 * make sure PCI enumeration runs and avoids resource conflicts.
            : 		 */
            : 		dev->enabled = true;
            : 		dev->hidden = true;
            : 		dev->ops = &amd_pcie_disabled_gpp_ops;
            : 	}
            : }
Could you add a comment somewhere (like in the commit-msg) that we don't scan downstream devices and therefore don't delay boot? Otherwise when reading this I wouldn't easily know why we couldn't just enable it in the chipset devicetree.