[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC

[Richard Spiegel (Code Review)]

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33624 )

Change subject: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC
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Patch Set 4:

(1 comment)

https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/acpi/cpu.asl 
File src/soc/amd/stoneyridge/acpi/cpu.asl:

https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/acpi/cpu.asl... 
PS3, Line 37: If (LGreaterEqual (\PCNT, 8))
> I'll have to double check, but when I used the original BIOS and booted to windows, there were some  […]

Look at RX-421BD
https://www.amd.com/en/products/embedded-r-series-soc
https://www.cpubenchmark.net/cpu.php?cpu=AMD+Embedded+R-Series+RX-421BD&...
Also RWEverything shows 4 groups of MSR (I believe hyperthread shares MSR).
So yes, 4 cores, 8 processing units (hyperthread)