[coreboot-gerrit] [XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports

[Cliff Huang (Code Review)]

Attention is currently required from: Matt DeVillier, Sean Rhodes.

Cliff Huang has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email )

Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
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Patch Set 7:

(1 comment)

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/85696/comment/7f324be1_e25cc58b?usp... :
PS5, Line 437: 	if (rp_type != PCIE_RP_PCH) {
> At the time, only PCH RP has power control for root port PHY. […]

Modphy gatting is supported only for PCIe root port under PCH in rtd3.c. The CPU PCIe root ports in older archecture like Tiger Lake Alder lake do not have this support. However, In the recent SoC architecture, all PCIe Root ports in PCD (i.e. PCIE_RP_PCH) and therefore, modPHY gating is supported for all RP ports.  Please see src/soc/intel/common/block/pcie/rtd3/chip.h for the comments regarding of  ext_pm_support.