[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Enable LPC generic IO decode range

[Johnny Lin (Code Review)]

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38994 )

Change subject: soc/intel/xeon_sp: Enable LPC generic IO decode range
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38994/1/src/soc/intel/xeon_sp/chip.... 
File src/soc/intel/xeon_sp/chip.h:

https://review.coreboot.org/c/coreboot/+/38994/1/src/soc/intel/xeon_sp/chip.... 
PS1, Line 89: 	uint32_t gen3_dec;
> These ranges may or may not be defined in mainboard devicetree.cb file. […]

When they are not defined the values would be zero, which are the default values of these registers. So it's still fine if the common LPC function pch_enable_lpc() writes zero to them.
I also checked icelake and skylake's implementation they do not handle undefined case, either.