Attention is currently required from: Jarried Lin.
Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86380?usp=email )
Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0 ......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/blobs/+/86380/comment/381656cc_ebc180f6?usp=em... : PS2, Line 7: 16189.0.0 Why not use the binary built from the ChromeOS FW branch, which should be more stable?
https://review.coreboot.org/c/blobs/+/86380/comment/86b9af55_b351365f?usp=em... : PS2, Line 7: update mtk_fsp_ramstage to version: 16189.0.0 `Update mtk_fsp_ramstage to 16189.0.0`
https://review.coreboot.org/c/blobs/+/86380/comment/aad3f6b1_ea4f09f8?usp=em... : PS2, Line 13: rauru We don't need this in the rauru FW branch, because ChromeOS builds always build mtk-fsp from source.
File soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt:
https://review.coreboot.org/c/blobs/+/86380/comment/e1ba2a64_0e985b9d?usp=em... : PS2, Line 5: Include Included
https://review.coreboot.org/c/blobs/+/86380/comment/f51c8c97_c685a42e?usp=em... : PS2, Line 7: - CL:*7980492 mt8196/kraken_v3: Call dsb() after writing to CSRAM The CL order in the v1.0 release notes is the opposite: from latest to oldest. Please be consistent.