[coreboot-gerrit] Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Reka Norman, Sridhar Siricilla, Balaji Manigandan, Krishna P Bhat D.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 )

Change subject: util/spd_tools: Add LP5 support for ADL
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Patch Set 8: Code-Review+2

(2 comments)

Patchset:

PS8:
> The lp4x SPD tools support Cezanne (AMD) as well, and the ddr4 tools support Picasso (AMD) too, so t […]

Reka, +1 to your assessment. Until we know the MRC requirements for other SoC vendors, this is as general as it can get. I will work with you when LP5 is adopted by AMD mainboards.

Nick,

As Tim mentioned, both Zork and Guybrush has been using the SPD tools.

File util/spd_tools/src/spd_gen/lp5.go:

https://review.coreboot.org/c/coreboot/+/58679/comment/b907fb44_dbd860e1 
PS5, Line 18: 	DensityPerDieGb    int
> Yes, LP5 only supports one channel per die. […]

Not for this CL: Does that mean we can remove the RAM_CHANNEL_SELECT GPIO strap? Something to check out in the schematics.