[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Disable isoch operation for performance

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48738 )

Change subject: soc/intel/xeon_sp/cpx: Disable isoch operation for performance
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soc/intel/xeon_sp/cpx: Disable isoch operation for performance

Isochronous operation negatively impacts memory performance, as
per Intel MLC (Memory Latency Checker) benchmark results. Thus,
disable isochronous operation, like analogous UEFI firmware does.
The MLC results after disabling isoch:

"--max_bandwidth"
ALL Reads :         106948.17
3:1 Reads-Writes :  101580.46
2:1 Reads-Writes :  100523.26
1:1 Reads-Writes :  99059.44
Stream-triad like : 97762.47

"--peak_injection_bandwidth"
ALL Reads :         105724.3
3:1 Reads-Writes :  100655.8
2:1 Reads-Writes :  99463
1:1 Reads-Writes :  98708
Stream-triad like : 91515

The MLC results before disabling isoch:

"--max_bandwidth"
ALL Reads :         88824.96
3:1 Reads-Writes :  94820.81
2:1 Reads-Writes :  94867.53
1:1 Reads-Writes :  92567.36
Stream-triad like : 91900.43

"--peak_injection_bandwidth"
ALL Reads :         88859.6
3:1 Reads-Writes :  94064
2:1 Reads-Writes :  94186.2
1:1 Reads-Writes :  92516.1
Stream-triad like : 85147.4

TEST=On OCP Delta Lake, verify that MLC benchmark results have
improved.

Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4
Signed-off-by: Johnny Lin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738
Reviewed-by: Marc Jones 
Reviewed-by: Jonathan Zhang 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marc Jones: Looks good to me, approved
  Jonathan Zhang: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index 6f47a30..e423d0a 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -163,5 +163,8 @@
    m_cfg->VtdSupport = config->vtd_support;
    m_cfg->X2apic = config->x2apic;

+	/* Disable ISOC */
+	m_cfg->isocEn = 0;
+
    mainboard_memory_init_params(mupd);
 }