Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40259 )
Change subject: soc/intel/common: Add _DSM methods for LPIT table ......................................................................
Patch Set 2: Code-Review+1
(7 comments)
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@7 PS1, Line 7: src/
Remove.
Done
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@10 PS1, Line 10: in LPIT table. This provides OSPM with s0ix entry and exit
Is that defined in the ACPI spec? Why is it not done in the operating system?
I have realized that my description was not accurate. I corrected it now.
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@12 PS1, Line 12: s0ix
S0ix
Done
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@9 PS1, Line 9: This patch adds support for Low Power S0 idle Device Specific Method : in LPIT table. This provides OSPM with s0ix entry and exit : hooks. These LPIT S0ix entry and exit hooks call platform specific : methods (MS0X) for s0ix entry and exit, when they exist
Please re-flow for 72/75 charcaters per line.
Done
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@12 PS1, Line 12: methods (MS0X) for s0ix entry and exit, when they exist
Please add a dot/period at the end of sentences.
Done
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@13 PS1, Line 13:
Is this just boiler plate or is it actually doing something. […]
This is needed for a short term workaround. This will be included into dsdt.
https://review.coreboot.org/c/coreboot/+/40259/1//COMMIT_MSG@16 PS1, Line 16: BUILD to check if is successful
build is enough.
Done