Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17974
-gerrit
commit 2292956366f771d3c8091feba4018ecb425d7da9 Author: Arthur Heymans arthur@aheymans.xyz Date: Tue Dec 27 18:04:34 2016 +0100
[WIP] nb/i945/gma : Implement VESA mode on VGA output
This implements VESA mode on the VGA output to have native resolution in the payload. Currently this breaks textmode.
Change-Id: Ic1d365995b16a9033042ceb608592e970c263533 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/northbridge/intel/i945/gma.c | 335 +++++++++++++++++++++++++-------------- 1 file changed, 214 insertions(+), 121 deletions(-)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..1d0ba0b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -45,7 +45,8 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001
-#define BASE_FREQUENCY 100000 +#define BASE_FREQUENCY_LVDS 100000 +#define BASE_FREQUENCY_VGA 96000
static int gtt_setup(void *mmiobase) { @@ -174,7 +175,8 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, for (candp1 = 1; candp1 <= 8; candp1++) { u32 m = 5 * (candm1 + 2) + (candm2 + 2); u32 p = candp1 * pixel_p2; - u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY_LVDS * m, candn + 2); u32 dot = DIV_ROUND_CLOSEST(vco, p); u32 this_err = MAX(dot, target_frequency) - MIN(dot, target_frequency); @@ -214,7 +216,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + BASE_FREQUENCY_LVDS * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / (pixel_n + 2) / (pixel_p1 * pixel_p2));
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { @@ -393,15 +395,82 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, void *pmmio, unsigned int pgfx) { - int i; - u32 hactive, vactive; - u16 reg16; + struct edid edid; + struct edid_mode *mode; + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; + u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1, pixel_p2, pixel_n, pixel_m1, pixel_m2; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; u32 uma_size; + u16 reg16; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + uma_size = 0; + if (!(reg16 & 2)) { + uma_size = decode_igd_memory_size((reg16 >> 4) & 7); + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); + } + + for (i = 0; i < (uma_size - 256) / 4; i++) { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + + intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, edid_data, + sizeof(edid_data)); + decode_edid(edid_data, sizeof(edid_data), &edid); + mode = &edid.mode; + + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + vblank = mode->vbl; + hblank = mode->hbl; + vsync = mode->vspw; + hsync = mode->hspw; + hfront_porch = mode->hso; + vfront_porch = mode->vso;
- printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", - (u32)pmmio, piobase, pphysbase); + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + /* R = j, G = j, B = j. */ + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
- gtt_setup(pmmio); + write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio + PP_ON_DELAYS, 0); + write32(pmmio + PP_OFF_DELAYS, 0);
/* Disable VGA. */ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); @@ -410,153 +479,177 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, write32(pmmio + PIPECONF(0), 0); write32(pmmio + PIPECONF(1), 0);
- write32(pmmio + INSTPM, 0x800); - - vga_gr_write(0x18, 0); - - write32(pmmio + VGA0, 0x200074); - write32(pmmio + VGA1, 0x200074); + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
- write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); - write32(pmmio + DSPCLK_GATE_D, 0); - write32(pmmio + FW_BLC, 0x03060106); - write32(pmmio + FW_BLC2, 0x00000306); + target_frequency = mode->pixel_clock; + pixel_p2 = target_frequency <= 225000 ? 10 : 5;
- write32(pmmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY_VGA * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = MAX(dot, target_frequency) + - MIN(dot, target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < smallest_err) { + smallest_err = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } + } + } + }
- write32(pmmio + 0x7041c, 0x0); + if (smallest_err == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + }
- write32(pmmio + DPLL_MD(0), 0x3); - write32(pmmio + DPLL_MD(1), 0x3); - write32(pmmio + DSPCNTR(1), 0x1000000); - write32(pmmio + PIPESRC(1), 0x027f01df); + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY_VGA * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2));
- vga_misc_write(0x67); - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); + write32(pmmio + PF_WIN_POS(0), 0); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(pmmio + PF_CTL(0), 0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PFIT_PGM_RATIOS, 0); + write32(pmmio + PFIT_CONTROL, 0); + } else { + write32(pmmio + PIPESRC(0), (639 << 16) | 399); + write32(pmmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(pmmio + PFIT_CONTROL, PFIT_ENABLE); + }
- for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); + mdelay(1);
- // Disable screen memory to prevent garbage from appearing. - vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + write32(pmmio + DSPCNTR(1), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_A | DISPPLANE_GAMMA_ENABLE);
mdelay(1); - write32(pmmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_VGA_MODE_DIS - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(0), (pixel_n << 16) | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); mdelay(1); - write32(pmmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_VGA_MODE_DIS - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); - - write32(pmmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); - - write32(pmmio + HTOTAL(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(pmmio + HBLANK(0), - ((hactive - 1) << 16) + write32(pmmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); + write32(pmmio + HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); + write32(pmmio + HBLANK(0), ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(pmmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1));
- write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(pmmio + VBLANK(0), ((vactive - 1) << 16) + write32(pmmio + VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(pmmio + VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(pmmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); - - write32(pmmio + PF_WIN_POS(0), 0); - - write32(pmmio + PIPESRC(0), (639 << 16) | 399); - write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(pmmio + PFIT_CONTROL, 0x0); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1));
mdelay(1);
- write32(pmmio + FDI_RX_CTL(0), 0x00002040); - mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x80002050); - write32(pmmio + FDI_TX_CTL(0), 0x00044000); - mdelay(1); - write32(pmmio + FDI_TX_CTL(0), 0x80044000); - write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio + DSPPOS(0), 0); + + /* Backlight init just in case a LVDS display is connected too */ + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC, 0x011d011a); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC_SELF, 0x0001003f); + write32(pmmio + FW_BLC, 0x011d0109); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight);
- write32(pmmio + VGACNTRL, 0x0); - write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_A | DISPPLANE_GAMMA_ENABLE); mdelay(1);
+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE); write32(pmmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); - - write32(pmmio + DSPFW3, 0x7f3f00c1); - write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); - write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); - write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH));
- /* Set up GTT. */ - - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); - uma_size = 0; - if (!(reg16 & 2)) { - uma_size = decode_igd_memory_size((reg16 >> 4) & 7); - printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - } + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET);
- for (i = 0; i < (uma_size - 256) / 4; i++) - { - outl((i << 2) | 1, piobase); - outl(pphysbase + (i << 12) + 1, piobase + 4); - } + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
/* Clear interrupts. */ write32(pmmio + DEIIR, 0xffffffff); write32(pmmio + SDEIIR, 0xffffffff); - write32(pmmio + IIR, 0xffffffff); - write32(pmmio + IMR, 0xffffffff); - write32(pmmio + EIR, 0xffffffff);
- vga_textmode_init(); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4);
+ set_vbe_mode_info_valid(&edid, pgfx); + } else { + vga_misc_write(0x67); + write32(pmmio + VGACNTRL, 0x00c4008e); + vga_textmode_init(); + } return 0; - }
/* compare the header of the vga edid header */