Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Kco... File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Kco... PS1, Line 26: SOC_INTEL_COMMON_BLOCK_ACPI
Should go in as a separate change?
Ack
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Mak... File src/soc/intel/alderlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Mak... PS1, Line 20: bootblock-y += gpio.c : romstage-y += gpio.c : ramstage-y += gpio.c : smm-y += gpio.c
I think these files are typically arranged in groups based on stages.
Ack
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 36: This layout matches the Linux kernel pinctrl map for ADL at: : * linux/drivers/pinctrl/intel/pinctrl-alderlake.c
i know its there at some sandbox or chromium repo for sure
Ack