[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHI...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33189 )

Change subject: soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/33189/1/src/soc/intel/icelake/graphics.c 
File src/soc/intel/icelake/graphics.c:

https://review.coreboot.org/#/c/33189/1/src/soc/intel/icelake/graphics.c@48 
PS1, Line 48: DDI_A_4_LANES
> > > So it's just more code to copy-paste later. Probably without […]

Those registers are applicable for ICL as well. And also how do you know that we haven't check if removing those code not giving any problem ?

I guess comments are enough to understand the problem without those GT programming in coreboot

/*
 * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
 * This will allow the kernel to use 4-lane eDP links properly
 * if the VBIOS or GOP driver do not execute.
 */

It won't cause any CB issue rather kerner display won't come over eDP when we skip executing GOP/VBIOS, which is typically happening during normal mode.

More details here: https://review.coreboot.org/13690