Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49169 )
Change subject: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function ......................................................................
[UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function
It was being run twice, in both bootblock and romstage. Using Lynxpoint as a reference, reorder the code so that it is only run once.
Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 37 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/49169/1
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..f594a9f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -3,8 +3,15 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <types.h> + #include "pch.h"
+static void map_rcba(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); +} + static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -33,13 +40,14 @@
void bootblock_early_southbridge_init(void) { + map_rcba(); enable_spi_prefetching_and_caching(); - - early_pch_init(); - enable_port80_on_lpc(); set_spi_speed();
/* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc_decode(); + mainboard_pch_lpc_setup(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6daafe0..f684a96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -216,26 +216,6 @@ write_iobp(0xec000780, 0x02000020); }
-static void pch_enable_bars(void) -{ - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - - /* Enable GPIO functionality. */ - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -} - -static void pch_generic_setup(void) -{ - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ -} - static void pch_enable_gbe(void) { uint8_t wanted_buc; @@ -260,7 +240,27 @@ } }
-static void pch_enable_lpc_decode(void) +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ +} + +void pch_enable_lpc_decode(void) { /* * Enable some common LPC IO ranges: @@ -298,18 +298,13 @@
void early_pch_init(void) { - pch_enable_lpc_decode(); - - mainboard_pch_lpc_setup(); + pch_enable_gbe();
pch_enable_bars();
- pch_generic_setup(); - - pch_enable_gbe(); - setup_pch_gpios(&mainboard_gpio_map);
- if (ENV_ROMSTAGE) - enable_smbus(); + pch_generic_setup(); + + enable_smbus(); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index dcab839..3b91e31 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,6 +56,7 @@ /* Optional mainboard hook to do additional LPC configuration or to override what is set up by default. */ void mainboard_pch_lpc_setup(void); +void pch_enable_lpc_decode(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void);