[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL

[Kapil Porwal (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal.

Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 )

Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL
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Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69571/comment/2fcc2d82_9577e955 
PS2, Line 21: YES
> It is just a debug message. A port of ADL CL.

It is the output of an existing API (is_spi_wp_cse_ro_en).

File src/soc/intel/meteorlake/me.c:

https://review.coreboot.org/c/coreboot/+/69571/comment/04fb09f0_c617b8fe 
PS2, Line 186: hfsts1.fields.mfg_mode
> Thanks Sridhar & Subrata. I will port both CLs (CB:69286 & CB:69324) once they are merged.

Rebased on top of MTL CL CB:69578