[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/anahera: Disable autonomous GPIO power management

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58695 )

Change subject: mb/google/brya/anahera: Disable autonomous GPIO power management
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mb/google/brya/anahera: Disable autonomous GPIO power management

With cr50 fw 0.3.22 or older version, it needs to disable autonomous
GPIO power management and then can update cr50 fw successfully.

BUG=b:202246591
TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage.

Signed-off-by: Wisley Chen 
Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/anahera/overridetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 0225f6c..7d003b3 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -22,6 +22,17 @@
    end
 end
 chip soc/intel/alderlake
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |