Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... PS5, Line 142: set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
Where's that different mechanism for NEM documented?
In general NEM mode and MTRR details its part of SDM and product BWG for anything more specific, you can find at public intel domain.
If it would be that easy to set up MTRRs from within NEM why does the ROMCC code and the postcar stage code update MTRRs only with NEM disabled?
postcar stage setting up MTRR with DRAM resources after we have initialized DIMM and main memory is available. Its recommended to tear down the car and move into main memory as soon as its available hence NEM mode existed and postcar stage sets new MTRR snapshots with 2 MTRR types
1. ROM cache 2. top of ram cache
why do we want to live into NEM mode when main memory is available.