Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48528 )
Change subject: soc/amd/cezanne: Add PSP integration for cezanne ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg File src/soc/amd/cezanne/fw.cfg:
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg@... PS6, Line 11: #4? : PSPNVRAM_FILE PspNvramCZN_2.bin I don't believe this should be an actual file. Although we used to include it for older devices, it's space the PSP uses for fTPM info AFAIK. And it's simply erased space in the flash. I confirmed it's all FFs in Majolica's image.
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg@... PS6, Line 28: PSP_MP2FW1_FILE TypeId0x125_MP2WALLE_CZN.sbin I don't know what this is. I'm not seeing a FW name that looks like it in the Cezanne PI. And 125 doesn't sound right because the type field is only 8 bits. In Majolica's UEFI image I only see a single MP2 FW file.
https://review.coreboot.org/c/coreboot/+/48528/6/src/soc/amd/cezanne/fw.cfg@... PS6, Line 54: PspNvramCZN_4.bin This isn't correct. However we should be reserving space for the RPMC and not passing a file in.