[coreboot-gerrit] Patch merged into coreboot/master: x86: prepare cache-as-ram to allow multiple stages

the following patch was just integrated into master:
commit dd6fa93dedc402cae65a333f5dff3d3c1a12f0c6
Author: Aaron Durbin 
Date:   Thu Sep 24 12:18:07 2015 -0500

x86: prepare cache-as-ram to allow multiple stages

In order to do a verification of romstage on x86 one needs to
    run verstage which verifies romstage (and the memory init code).
    However, x86 doesn't have SRAM like every other modern SoC so
    managing the cache-as-ram region is especially critical.

First move all of the "shared" objects to the beginning of
    the .car.data section. This change then ensures that each stage
    using car.ld to link has the same consistent view of the addresses
    of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can
    be unique per stage. However, these variables are expected to have
    a value of zero at the start of each stage. In order to allow a
    stage to provide those semantics outside of the initial cache-as-arm
    setup routine add _car_global_start and _car_global_end symbols.
    Those symbols can be used to clear the CAR_GLOBALs for that stage.

Note that the timestamp region can't be moved out similarly to the
    pre-ram cbmem console because the object storage of the timestamp
    cache is used *after* cache-as-ram is torn down to indicate if the
    cache should be used or not. Therefore, that timestamp needs to
    migrated to ram. A logic change in src/lib/timestamp.c could
    alleviate this requirement, but that task wasn't tackled in this
    patch.

BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Built and booted glados.

Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61
    Signed-off-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/11740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi

See http://review.coreboot.org/11740 for details.

-gerrit