Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, Shelley Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31250
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ......................................................................
soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
FSP-S is currently configuring GPIOs that it should not. This results in issues where mainboard devices don't behave as expected e.g. host unable to receive TPM interrupts as the pad for the interrupt is re-configured as something else.
Until FSP-S is fixed, this change adds a workaround by reconfiguring GPIOs after FSP-S is run.
All mainboards need to call cnl_configure_pads instead of gpio_configure_pads so that SoC code can maintain a reference to the GPIO table and use that to re-configure GPIOs after FSP-S is run.
This change is currently not made for CNL-PCH-H since I do not see any boards with PCH-H that care about this. If required, the change can be easily extended to enable the same logic.
BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/gpio.h 3 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31250/3