[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69689 )

Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init
......................................................................

mb/google/herobrine: Implement mainboard_needs_pcie_init

Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links.  When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.

BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/herobrine/mainboard.c
M src/soc/qualcomm/common/include/soc/pcie.h
2 files changed, 42 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69689/1

diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c
index ece6d68..881ed44 100644
--- a/src/mainboard/google/herobrine/mainboard.c
+++ b/src/mainboard/google/herobrine/mainboard.c
@@ -8,10 +8,12 @@
 #include <delay.h>
 #include <device/device.h>
 #include <device/mmio.h>
+#include <ec/google/chromeec/ec.h>
 #include <edid.h>
 #include <soc/clock.h>
 #include <soc/display/mdssreg.h>
 #include <soc/display/edp_ctrl.h>
+#include <soc/pcie.h>
 #include <soc/qupv3_config_common.h>
 #include <soc/qup_se_handlers_common.h>
 #include <soc/qcom_qup_se.h>
@@ -82,6 +84,25 @@
    }
 }

+bool mainboard_needs_pcie_init(void)
+{
+	uint32_t sku = sku_id();
+
+	if (sku == CROS_SKU_UNKNOWN) {
+		printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku);
+		return true;
+	} else if (sku == CROS_SKU_UNPROVISIONED) {
+		printk(BIOS_WARNING, "Unprovisioned SKU (%#x); assuming PCIe", sku);
+		return true;
+	}
+
+	if ((sku & BIT(0)) == 2)
+		return true;
+
+	/* Otherwise, eMMC */
+	return false;
+}
+
 static void mainboard_init(struct device *dev)
 {
    /* Configure clock for eMMC */
diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h
index 09ea671..b2f9e45 100644
--- a/src/soc/qualcomm/common/include/soc/pcie.h
+++ b/src/soc/qualcomm/common/include/soc/pcie.h
@@ -221,5 +221,6 @@
 void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg);
 void qcom_pci_domain_read_resources(struct device *dev);
 void qcom_setup_pcie_host(struct device *dev);
+bool mainboard_needs_pcie_init(void);

#endif