[coreboot-gerrit] Change in ...coreboot[master]: mb/ocp/wedge100s: Use the new IPMI driver

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33489

Change subject: mb/ocp/wedge100s: Use the new IPMI driver
......................................................................

mb/ocp/wedge100s: Use the new IPMI driver

* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address

Tested on Wedge100s.

Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph 
---
M src/mainboard/ocp/wedge100s/Kconfig
M src/mainboard/ocp/wedge100s/devicetree.cb
M src/mainboard/ocp/wedge100s/romstage.c
3 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33489/1

diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index bd5e665..491829a 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -16,6 +16,7 @@
    select MAINBOARD_HAS_TPM1
    select DRIVERS_UART_8250IO
    select SUPERIO_ITE_IT8528E
+	select IPMI_KCS

config VBOOT
    select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
index 48410ba..e9161ce 100644
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ b/src/mainboard/ocp/wedge100s/devicetree.cb
@@ -60,6 +60,9 @@
    			device pnp 6e.18 off end
    			device pnp 6e.19 off end
    		end	#superio/ite/it8528e
+			chip drivers/ipmi
+				device pnp ca2.0 on end         # IPMI KCS
+			end
    	end # LPC Bridge
    	device pci 1f.2 on end # SATA Controller
    	device pci 1f.3 on end # SMBus Controller
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index 7fdc981..108d7a1 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -38,6 +38,10 @@
    pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC,
    		   (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1);

+	/* Decode IPMI KCS */
+	pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
+			   (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1);
+
    if (CONFIG(CONSOLE_SERIAL))
    	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);