Mono Moosbart (mono@posteo.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7990
-gerrit
commit 532c5947fd4ca2a343ac0c55c97deaaa5c3b3295 Author: Mono mono@posteo.de Date: Wed Dec 31 01:52:27 2014 +0100
i82801gx: remove wrong code from pci bridge init.
This code uses missleading register name PCI_MIN_GNT defined in pci_def.h with 0x3e. However this device has no register with this name. Moreover, this device's register at offset 0x3e has the name BCTRL defined in i82801gx.h. Right above this removed code, in line 41-44, bits 0 and 1 at offset 0x3e (BCTRL) are cleared disabling Parity Error Response and SERR#. The removed code then enables SERR# and ISA.
Other sounthbridges maybe use the same wrong code (lynxpoint, bd82x6x).
Change-Id: I61270441a56067e4255c75d39428258dc39ffaef Signed-off-by: Axel Holewa mono@posteo.de --- src/southbridge/intel/i82801gx/pci.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 0f372e7..90d9107 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -49,9 +49,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8);
- /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900;