[coreboot-gerrit] Change in coreboot[master]: xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices

[Johnny Lin (Code Review)]

Attention is currently required from: Marc Jones, Jonathan Zhang, Jingle Hsu, Morgan Jang, Patrick Rudolph, Tim Chu.
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49893 )

Change subject: xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices
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Patch Set 3:

(1 comment)

File src/soc/intel/xeon_sp/cpx/romstage.c:

https://review.coreboot.org/c/coreboot/+/49893/comment/dc723148_dfdcd3c5 
PS3, Line 24: uint32_t __weak mainboard_skt_memory_max_capacity_mib(void) { return 0; }
> Does the really need a mainboard override? This should have a good default value for CPX.

In case this value is different among different CPX CPU models, so mainboard has a chance to set its own value accordingly. If it's 0 smbios.c would still calculate the current installed memory DIMMs sizes as the maximum memory capacity for type 16.