[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/mtl: Enable SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kane Chen, Kapil Porwal, Tarun.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79654?usp=email )

Change subject: soc/intel/mtl: Enable SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE
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Patch Set 2:

(1 comment)

Patchset:

PS2:
> lets wait for sometime to land this CL as I'm not clear if any intruder is trying to flip the WPD status and if we follow the trap and clear the SMI which is not correct IMO.

we can land this cl based on the debug data

Disabling Write Protection (WP) without first clearing the System Management Interrupt (SMI) can lead to issues. When setting WP from 0 to 1, the SMI bit is also set to 1. If we then attempt to disable WP (change the WPD bit) while the SMI bit remains at 1, we are effectively trying to clear the SMI bit using software. However, the SMI bit (1C) can only be cleared by hardware through a De-assert Synchronous SMI message.