Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kane Chen, Kapil Porwal, Tarun.
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1 comment:
Patchset:
Patch Set #2:
lets wait for sometime to land this CL as I'm not clear if any intruder is trying to flip the WPD status and if we follow the trap and clear the SMI which is not correct IMO.
we can land this cl based on the debug data
Disabling Write Protection (WP) without first clearing the System Management Interrupt (SMI) can lead to issues. When setting WP from 0 to 1, the SMI bit is also set to 1. If we then attempt to disable WP (change the WPD bit) while the SMI bit remains at 1, we are effectively trying to clear the SMI bit using software. However, the SMI bit (1C) can only be cleared by hardware through a De-assert Synchronous SMI message.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76
Gerrit-Change-Number: 79654
Gerrit-PatchSet: 2
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