Attention is currently required from: Felix Singer, Nico Huber, Matt DeVillier, Tim Wawrzynczak, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Frans Hendriks, Matt DeVillier, Tim Wawrzynczak, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52139
to look at the new patch set (#8).
Change subject: docs: correct and rewrite documentation regarding n/c / unused pads ......................................................................
docs: correct and rewrite documentation regarding n/c / unused pads
Intel PDGs starting from Skylake / Sunrise Point state that, different from the general recommendation in digital electronics, unconnected GPIOs defaulting to GPIO mode do explicitly not require termination.
The reason for this is, that is that these GPIOs have the `GPIORXDIS` bit set, which effectively disconnects the pad from the internal logic by disabling the input buffer.
This bit - besides `GPIOTXDIS` - can also be set explicitly by using the gpio macro `PAD_NC(pad, NONE)`.
In some cases, a pull resistor may be required due to bad board design or when a vendor sets the RX/TX disable bits together with a pull resistor and schematics are not available to check if the pad is really unconnected or just unused. In this case the pull resistor should be kept.
<FIXME> add info an native function
Rewrite the documentation to reflect these new findings.
Also clarify the comment in soc/intel gpio code accordingly.
Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M Documentation/getting_started/gpio.md M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 41 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/52139/8