[coreboot-gerrit] Change in coreboot[master]: soc/intel: Fix regression with hidden PCI devices

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34285 )

Change subject: soc/intel: Fix regression with hidden PCI devices
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Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34285/7/src/device/device_const.c 
File src/device/device_const.c:

https://review.coreboot.org/c/coreboot/+/34285/7/src/device/device_const.c@2... 
PS7, Line 243: 	printk(BIOS_ERR, "BUG: %s requests hidden 00:%02x.%u\n", func, devfn >> 3, devfn & 7);
> I get it now. It's coming back to be w.r.t. the p2sb. However, that device is unhidden after fsp-s. […]

It was in the static devicetree, but failing ID query it was removed from the topology links pcidev_path_behind() traverses. The workaround below traverses linked list of all devices, and hidden PCI devices are still present there.

Somewhere I read these hidden PCI devices will respond to all PCI config reads with 0xff's while accepting all PCI config writes. Might have been Nico or Furquan who found some details about this.

Conclusion: PCI config reads are not allowed, but PCI config writes need to go through??