Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33189 )
Change subject: soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/33189/1/src/soc/intel/icelake/graphics.c File src/soc/intel/icelake/graphics.c:
https://review.coreboot.org/#/c/33189/1/src/soc/intel/icelake/graphics.c@48 PS1, Line 48: DDI_A_4_LANES
If it gets merged, it adds maintenance burden. If it's only for early […]
i don't understand your point, you are telling not to work on early soc right ? then how do we enable and validate early soc?
PCI enumeration is required because we might need to program GTTMMADR0 and GMADR to make use of sw rendering method even to bring chrome/chromium display on non-GT parts.
We are driving some initiatives where we can skip HW acceleration and still bring up display to continue our work.
Kindly have trust on us on working on early silicon and we will clean those code (Kconfig) without bothering community to clean the same once we have GT enable parts ready