Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46490 )
Change subject: intel/txt: Add `txt_get_chipset_dpr` function ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/46490/1/src/security/intel/txt/rams... File src/security/intel/txt/ramstage.c:
https://review.coreboot.org/c/coreboot/+/46490/1/src/security/intel/txt/rams... PS1, Line 237: MCH SA?
https://review.coreboot.org/c/coreboot/+/46490/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/46490/1/src/soc/intel/common/block/... PS1, Line 153: SA_DEV_ROOT On xeon_sp you have multiple SA (not sure on the terminology but they call it IIOs), on different PCI busses. Maybe add a TODO/NOTE comment?