[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Pass more SPI options to FSP.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )

Change subject: soc/intel/cannonlake: Pass more SPI options to FSP.
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/chip.h@41 
PS2, Line 41: #define SOC_INTEL_CML_SPI_DEV_MAX 3
> What does this represent? Generic SPI devices? PchSerialIoSpiMAX == 2 but this macro is 3. […]

CsPolarity and CsEnable are 2-field arrays where each field indicates each Chip select i.e. CS0 and CS1.

SerialIoSpiDefaultCsOutput selects the default chip select for each spi device i.e. SPI0, SPI1 and SPI2.

So, basically there are 3 GSPI buses and 2 Chip selects for each bus.