Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8555
-gerrit
commit 24a64c0381647eba01f02509fdf79b652c364683 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Feb 21 23:56:07 2015 +0200
AMD fam10: Fix add_more_links FIXME
One PCI function may contain upto 4 links, further links must be added to PCI function 4 on the same device.
To have support for 8 links starts with HT 3.0 specs?
There is no requirement that in dev->link_list the last element would have the highest link->link_num.
Also fix off-by-one error when allocating for more links.
Change-Id: If7ebdd1ad52653d3757b5930bd0a83e2cf2fcac6 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/northbridge/amd/amdfam10/northbridge.c | 56 ++++++++++++++++++------------ 1 file changed, 33 insertions(+), 23 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 4734522..b456e9d 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -176,18 +176,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #endif u32 max_devfn;
- if (link->link_num > 3) { - u32 regpos; - u32 reg; - regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 - reg = pci_read_config32(dev, regpos); - if(reg & 1) return max; // already ganged no sblink1 - - dev = get_node_pci(nodeid, 4); - } - /* Check for connected link. */ - link->cap = 0x80 + ((link->link_num & 3) * 0x20); + link->cap = 0x80 + (link->link_num * 0x20); if (!is_non_coherent_link(dev, link)) return max;
@@ -1175,17 +1165,34 @@ static void sysconf_init(device_t dev) // first node #endif }
+#if 0 +static void FIXME_add_more_links(); +{ + if (link->link_num > 3) { + u32 regpos; + u32 reg; + regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 + reg = pci_read_config32(dev, regpos); + if (reg & 1) return max; // already ganged no sblink1 + + dev = get_node_pci(nodeid, 4); + } +} +#endif + static void add_more_links(device_t dev, unsigned total_links) { struct bus *link, *last = NULL; - int link_num; + int link_num = -1;
- for (link = dev->link_list; link; link = link->next) + for (link = dev->link_list; link; link = link->next) { + if (link_num < link->link_num) + link_num = link->link_num; last = link; + }
if (last) { - int links = total_links - last->link_num; - link_num = last->link_num; + int links = total_links - (link_num + 1); if (links > 0) { link = malloc(links*sizeof(*link)); if (!link) @@ -1195,7 +1202,6 @@ static void add_more_links(device_t dev, unsigned total_links) } } else { - link_num = -1; link = malloc(total_links*sizeof(*link)); memset(link, 0, total_links*sizeof(*link)); dev->link_list = link; @@ -1337,15 +1343,19 @@ static void cpu_bus_scan(device_t dev) cdb_dev = pci_probe_dev(NULL, pbus, PCI_DEVFN(devn, fn)); } - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - } - if (cdb_dev) { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 8); }
+ /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (cdb_dev) + add_more_links(cdb_dev, 4); + + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 4)); + if (cdb_dev) + add_more_links(cdb_dev, 4); + cores_found = 0; // one core cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); int enable_node = cdb_dev && cdb_dev->enabled;