Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75585?usp=email )
Change subject: mb/google/myst: Add PSP verstage callbacks ......................................................................
mb/google/myst: Add PSP verstage callbacks
Lay the groundwork to prepare for enabling PSP verstage. This change adds PSP verstage callback to enable eSPI, TPM etc.
BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled.
Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/myst/Makefile.inc M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/verstage.c 3 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/75585/1
diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 54d4f30..9a8f8d8 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -9,6 +9,8 @@ ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c + subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index 3ef89ca..74839fa 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -8,5 +8,6 @@ romstage-y += tpm_tis.c
verstage-y += tpm_tis.c +verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c
smm-y += smihandler.c diff --git a/src/mainboard/google/myst/verstage.c b/src/mainboard/google/myst/verstage.c new file mode 100644 index 0000000..2320106 --- /dev/null +++ b/src/mainboard/google/myst/verstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio.h> +#include <arch/io.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <psp_verstage.h> +#include <security/vboot/vboot_common.h> +#include <soc/espi.h> +#include <soc/southbridge.h> + +void verstage_mainboard_early_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + variant_early_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +} + +void verstage_mainboard_espi_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + variant_espi_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); + + espi_switch_to_spi1_pads(); +} + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + variant_tpm_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +}