Jonathan A. Kollasch (jakllsch@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3975
-gerrit
commit 969b75bd423b7af2192b24dd4803a5c61baa3d6c Author: Jonathan A. Kollasch jakllsch@kollasch.net Date: Tue Oct 15 16:45:51 2013 -0500
winent-mb6047: initial WIN Enterprises MB-60470 board port
What works: - ACPI interrupt routing for onboard devices - onboard devices including USBs, ATAs, NICs, COM1
What almost works: - SMI720 VGA BIOS needs forthcoming VGA BIOS hooks in SeaBIOS to work
Untested: - Interrupt Line Register interrupt routing - PIRQ interrupt routing - MPBIOS/MPTABLE interrupt routing - unpopulated on board revision 1A AC97 audio - unpopulated PCI-E x16 slot - unpopulated ExpressCard slot - HT expansion board
Thanks to WIN Enterprises for providing boards.
Change-Id: I7787f89b3ab454b668c3b75d0d1cde55b8d53c48 Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net --- src/mainboard/winent/Kconfig | 4 + src/mainboard/winent/mb6047/Kconfig | 30 +++- src/mainboard/winent/mb6047/acpi_tables.c | 16 -- src/mainboard/winent/mb6047/devicetree.cb | 45 ++--- src/mainboard/winent/mb6047/dsdt.asl | 190 +++++++-------------- src/mainboard/winent/mb6047/get_bus_conf.c | 67 +------- src/mainboard/winent/mb6047/irq_tables.c | 32 ---- src/mainboard/winent/mb6047/mptable.c | 46 +---- src/mainboard/winent/mb6047/resourcemap.c | 266 ----------------------------- src/mainboard/winent/mb6047/romstage.c | 45 ++--- 10 files changed, 126 insertions(+), 615 deletions(-)
diff --git a/src/mainboard/winent/Kconfig b/src/mainboard/winent/Kconfig index 4c13a82..28c3360 100644 --- a/src/mainboard/winent/Kconfig +++ b/src/mainboard/winent/Kconfig @@ -21,11 +21,15 @@ if VENDOR_WINENT choice prompt "Mainboard model"
+config BOARD_WINENT_MB6047 + bool "MB6047" + config BOARD_WINENT_PL6064 bool "PL6064"
endchoice
+source "src/mainboard/winent/mb6047/Kconfig" source "src/mainboard/winent/pl6064/Kconfig"
config MAINBOARD_VENDOR diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index ddd7ed0..507340c 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -1,4 +1,4 @@ -if BOARD_TYAN_S2891 +if BOARD_WINENT_MB6047
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -6,8 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 - select SOUTHBRIDGE_AMD_AMD8131 - select SUPERIO_WINBOND_W83627HF + select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -16,10 +15,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select CK804_USE_NIC + select CK804_USE_ACI + select SET_FIDVID
config MAINBOARD_DIR string - default tyan/s2891 + default winent/mb6047
config APIC_ID_OFFSET hex @@ -31,15 +33,15 @@ config SB_HT_CHAIN_ON_BUS0
config MAINBOARD_PART_NUMBER string - default "S2891" + default "MB6047"
config MAX_CPUS int - default 4 + default 2
config MAX_PHYSICAL_CPUS int - default 2 + default 1
config HT_CHAIN_UNITID_BASE hex @@ -53,4 +55,16 @@ config IRQ_SLOT_COUNT int default 11
-endif # BOARD_TYAN_S2891 +config CK804_PCI_E_X + int + default 0 + +config VGA_BIOS_ID + string + default "126f,0720" + +config VGA_BIOS_FILE + string + default "DM22383.ROM" + +endif # BOARD_WINENT_MB6047 diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 42d9152..1b59fbb 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -30,7 +30,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { - unsigned long apic_addr; device_t dev; struct resource *res;
@@ -53,21 +52,6 @@ unsigned long acpi_fill_madt(unsigned long current) pci_write_config32(dev, 0x84, 0x0000007d); #endif
- /* Write AMD 8131 two IOAPICs. */ - dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, - apic_addr, 0x18); - } - - dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); - if (dev) { - apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, - apic_addr, 0x1C); - } - /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 3d8c65e..09a062e 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -5,13 +5,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x10f1 0x2891 inherit + subsystemid 0x10de 0xcb84 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O + chip superio/winbond/w83627thg # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -35,20 +35,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Consumer IR - io 0x60 = 0x100 - end - device pnp 2e.7 off # Game port, MIDI, GPIO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, MIDI, GPIO1 device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI - device pnp 2e.b off # Hardware monitor + device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 - irq 0x70 = 5 + irq 0x70 = 0 end end end @@ -97,38 +91,27 @@ chip northbridge/amd/amdk8/root_complex # Root complex # end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI + device pci 4.0 on end # ACI device pci 4.1 off end # MCI device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 7.0 on end + # device pci 6.0 on end end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 device pci d.0 on end # PCI E 1 device pci e.0 on end # PCI E 0 register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide1_enable" = "0" register "sata0_enable" = "1" register "sata1_enable" = "1" end end device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end - device pci 9.1 on end - end - device pci 1.1 on end - end - end + device pci 18.0 on end # Link 2 == LDT 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/winent/mb6047/dsdt.asl b/src/mainboard/winent/mb6047/dsdt.asl index 1c8680b..aa04d81 100644 --- a/src/mainboard/winent/mb6047/dsdt.asl +++ b/src/mainboard/winent/mb6047/dsdt.asl @@ -24,7 +24,7 @@
DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { - #include "northbridge/amd/amdk8/util.asl" + #include "northbridge/amd/amdk8/util.asl"
/* For now only define 2 power states: * - S0 which is fully on @@ -32,7 +32,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) * Any others would involve declaring the wake up methods. */ Name (_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) - Name (_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + Name (_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) + + Name (PICM, 0x00) + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + }
/* Root of the bus hierarchy */ Scope (_SB) @@ -83,53 +88,80 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Return (Local3) }
+ #include "southbridge/nvidia/ck804/acpi/ck804.asl" + /* PCI Routing Table */ Name (_PRT, Package () { - /* Since source is 0, index is IRQ. */ - /* in ABCD, A=0, B=1, C=2, D=3 */ - /* SlotFFFF, ABCD, source, index */ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LLAS, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LLAS, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, _SB.PCI0.LUOH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, _SB.PCI0.LUEH, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LAUD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LMOD, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, _SB.PCI0.LPA0, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x00, _SB.PCI0.LSA0, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, _SB.PCI0.LSA1, 0x00 }, + Package (0x04) { 0x000AFFFF, 0x00, _SB.PCI0.LEMA, 0x00 }, })
Device (PCIL) { Name (_ADR, 0x00090000) Name (_UID, 0x00) - Name (_BBN, 0x01) Name (_PRT, Package () { - Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + /* onboard SM720 VGA */ + Package (0x04) { 0x0006FFFF, 0x00, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, _SB.PCI0.LNKB, 0x00 }, }) }
- /* 2:00 PCIe x16 SB IRQ 18 */ - Device (PE16) + Device (PEX0) { Name (_ADR, 0x000e0000) Name (_UID, 0x00) - Name (_BBN, 0x02) Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKB, 0x00 }, }) }
- /* 2:00 PCIe x4 SB IRQ 17 */ - Device (PE4) + Device (PEX1) { - Name (_ADR, 0x000e0000) + Name (_ADR, 0x000d0000) + Name (_UID, 0x00) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKC, 0x00 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x000c0000) Name (_UID, 0x00) - Name (_BBN, 0x02) Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x000b0000) + Name (_UID, 0x00) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKA, 0x00 }, }) }
@@ -172,110 +204,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Return (TMP) } } - - /* Parallel port */ - Device (LP0) - { - Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - FixedIO (0x0378, 0x10) - IRQNoFlags () {7} - }) - Return (TMP) - } - } - - /* Floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - FixedIO (0x03F0, 0x08) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } - } - } - - /* AMD 8131 PCI-X tunnel */ - Device (PCI2) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) - Name (_UID, 0x00) - Name (_BBN, 0x40) - - /* There is no _PRT Here because I don't know what to - * put in it. Since the 8131 has its own APIC, it - * isn't wired to other IRQs. */ - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - }) - /* Methods bellow use SSDT to get actual MMIO regs - The IO ports are from 0xd00, optionally an VGA, - otherwise the info from MMIO is used. - _SB.GXXX(node, link) - */ - Concatenate (_SB.GMEM (0x00, 0x02), BUF0, Local1) - Concatenate (_SB.GIOR (0x00, 0x02), Local1, Local2) - Concatenate (_SB.GWBN (0x00, 0x02), Local2, Local3) - Return (Local3) - } - - /* Channel A PCIX 133 */ - Device (PCXF) - { - Name (_ADR, 0x00000000) - Name (_UID, 0x00) - Name (_BBN, 0x41) - Name (_PRT, Package () { - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, - Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ - Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, - Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, - }) - } - - /* Channel B PCIX 100 */ - Device (PCXS) /* Onboard NIC */ - { - Name (_ADR, 0x00010000) - Name (_UID, 0x00) - Name (_BBN, 0x42) - Name (_PRT, Package () { - Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, - Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, - Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, - }) } } } diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index e94c608..5b96b05 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -3,9 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> -#endif
#include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> @@ -18,40 +16,17 @@ unsigned char bus_ck804_2; //3 unsigned char bus_ck804_3; //4 unsigned char bus_ck804_4; //5 unsigned char bus_ck804_5; //6 -unsigned char bus_8131_0; //7 -unsigned char bus_8131_1; //8 -unsigned char bus_8131_2; //9 -unsigned char bus_coproc_0; unsigned apicid_ck804; -unsigned apicid_8131_1; -unsigned apicid_8131_2;
unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000000, - 0x0000200, - 0x0000100, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, - 0x20202020, - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, };
-unsigned sbdn3; -unsigned coprocdn; - static unsigned get_bus_conf_done = 0;
void get_bus_conf(void) @@ -79,8 +54,6 @@ void get_bus_conf(void) sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn;
- sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain - bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
/* CK804 */ @@ -120,45 +93,7 @@ void get_bus_conf(void) sbdn + 0x0e); }
- bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3, 0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_2++; - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); - - bus_8131_1 = bus_8131_0 + 1; - bus_8131_2 = bus_8131_0 + 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3 + 1, 0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); - - bus_8131_2 = bus_8131_1 + 1; - } - - if (sysconf.pci1234[2] & 1) { - bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; - coprocdn = (sysconf.hcdn[2] & 0xff); - } - /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS - apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; -#endif + apicid_base = get_apicid_base(1); apicid_ck804 = apicid_base + 0; - apicid_8131_1 = apicid_base + 1; - apicid_8131_2 = apicid_base + 2; } diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c index d584dbb..25da282 100644 --- a/src/mainboard/winent/mb6047/irq_tables.c +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -36,15 +36,6 @@ extern unsigned char bus_ck804_2; //3 extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_5; //6 -extern unsigned char bus_8131_0; //7 -extern unsigned char bus_8131_1; //8 -extern unsigned char bus_8131_2; //9 -extern unsigned char bus_coproc_0; - -extern unsigned sbdn3; -extern unsigned coprocdn; - -
unsigned long write_pirq_routing_table(unsigned long addr) { @@ -91,14 +82,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; -//pcix bridge - write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; -//co processor - if(sysconf.pci1234[2] & 1) { - write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - }
#if 0 //smbus @@ -133,21 +116,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) //Slot2 pci write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); pirq_info++; slot_num++; -//Slot3 PCIE x16 - write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); - pirq_info++; slot_num++; - -//Slot4 PCIX - write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); - pirq_info++; slot_num++; - -//Slot5 PCIX - write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); - pirq_info++; slot_num++; - -//Slot6 PCIX - write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); - pirq_info++; slot_num++; #endif
pirq->size = 32 + 16 * slot_num; diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index cb49434..26e79ca 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -11,14 +11,8 @@ extern unsigned char bus_ck804_2; //3 extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_5; //6 -extern unsigned char bus_8131_0; //7 -extern unsigned char bus_8131_1; //8 -extern unsigned char bus_8131_2; //9 extern unsigned apicid_ck804; -extern unsigned apicid_8131_1; -extern unsigned apicid_8131_2;
-extern unsigned sbdn3;
static void *smp_write_config_table(void *v) { @@ -60,22 +54,6 @@ static void *smp_write_config_table(void *v)
dword = 0x0000007d; pci_write_config32(dev, 0x84, dword); - - } - - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } }
} @@ -107,28 +85,8 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); }
-//Onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 - -//Channel B of 8131 - - -//Onboard Broadcom NIC - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 - } - -//Channel A of 8131 - -//Slot 4 PCIX 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 - } - -//Slot 3 PCIX 133/100/66 SoDIMM PCI - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 - } +//Onboard SM720 VGA + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x13); // 19
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/winent/mb6047/resourcemap.c b/src/mainboard/winent/mb6047/resourcemap.c deleted file mode 100644 index d76f1d6..0000000 --- a/src/mainboard/winent/mb6047/resourcemap.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Tyan S2891 needs a different resource map - * - */ - -static void setup_s2891_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} - diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 9cd3a4a..79bede8 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -16,12 +16,12 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include "superio/winbond/w83627thg/early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static void memreset_setup(void) { } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -35,12 +35,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) @@ -59,25 +61,13 @@ static void sio_setup(void) dword |= (1<<0) | (1<<1); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-#if 1 - /* s2891 has onboard LPC port 80 */ - /*Hope I can enable port 80 here - It will decode port 80 to LPC, If you are using PCI post code you can not do this */ - dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); -#endif }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, -#endif + DIMM0, 0, 0, 0, + DIMM1, 0, 0, 0, };
int needs_reset; @@ -96,25 +86,38 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// post_code(0x32);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_s2891_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); + +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { + msr_t msr; + /* Read FIDVID_STATUS */ + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + } #endif
needs_reset |= ht_setup_chains_x();