[coreboot-gerrit] Change in ...coreboot[master]: sb/intel/common: Add a function to cleanly lock down the SPI config

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33042

Change subject: sb/intel/common: Add a function to cleanly lock down the SPI config
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sb/intel/common: Add a function to cleanly lock down the SPI config

Currently SPI gets locked in ramstage/smm with updating the
g_ichspi_lock global variable. Some southbridges worked around it by
reinitializing SPI by calling spi_init();

Change-Id: Idc2340c74b95644c38ea88997d7dc6f2ec32e7e3
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/spi.h
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33042/1

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index c8e953e..2935d6b 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -1082,6 +1082,32 @@
 {
 }

+void spi_lock_down(void)
+{
+	uint8_t *rcrb; /* Root Complex Register Block */
+	uint32_t rcba; /* Root Complex Base Address */
+	ich9_spi_regs *ich9_spi;
+	ich7_spi_regs *ich7_spi;
+
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev = PCI_DEV(0, 31, 0);
+#else
+	struct device *dev = pcidev_on_root(31, 0);
+#endif
+
+	rcba = pci_read_config32(dev, 0xf0);
+	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
+	rcrb = (uint8_t *)(rcba & 0xffffc000);
+	if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
+		ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
+		writew_(readw_(&ich7_spi->spis) | HSFS_FLOCKDN, &ich7_spi->spis);
+	} else {
+		ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
+		writew_(readw_(&ich9_spi->hsfs) | HSFS_FLOCKDN, &ich9_spi->hsfs) ;
+	}
+	g_ichspi_lock = 1;
+}
+
 static const struct spi_ctrlr spi_ctrlr = {
    .xfer_vector = xfer_vectors,
    .max_xfer_size = member_size(ich9_spi_regs, fdata),
diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h
index fcc5cd8..5dbd723 100644
--- a/src/southbridge/intel/common/spi.h
+++ b/src/southbridge/intel/common/spi.h
@@ -34,5 +34,6 @@

void spi_finalize_ops(void);
 void intel_southbridge_override_spi(struct intel_spi_config *spi_config);
+void spi_lock_down(void);

#endif