[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/meteorlake: Disable 3-strike error

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74159 )

Change subject: soc/intel/meteorlake: Disable 3-strike error
......................................................................

soc/intel/meteorlake: Disable 3-strike error

This patch calls into API to disable 3-strike error on
Meteor Lake SoC based platform.

TEST=Able to build and boot google/rex to ChromeOS.
Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled

```
  localhost ~ # iotools rdmsr 0 0x1a4
  0x0000000000000900
```

Signed-off-by: Subrata Banik 
Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9
---
M src/soc/intel/meteorlake/cpu.c
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74159/1

diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c
index 691f50d..50ff3b2 100644
--- a/src/soc/intel/meteorlake/cpu.c
+++ b/src/soc/intel/meteorlake/cpu.c
@@ -104,6 +104,9 @@
 /* All CPUs including BSP will run the following function. */
 void soc_core_init(struct device *cpu)
 {
+	/* Disable 3-strike error */
+	disable_three_strike_error();
+
    /* Clear out pending MCEs */
    /* TODO(adurbin): This should only be done on a cold boot. Also, some
     * of these banks are core vs package scope. For now every CPU clears