Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )
Change subject: mainboard/google/volteer: Enable long cr50 ready pulses ......................................................................
Patch Set 12:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... PS12, Line 35: mainboard_update_s0ix_disable_mask
I think the intention may be more clear by updating the UPDs directly.
We have generally avoided overwriting the FSP UPDs directly in mainboard and instead used the SoC chip configs so that the SoC alone can update the UPDs. (I honestly think that we should drop the callback `mainboard_silicon_init_params` from SoC).
https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... PS12, Line 46: gpio_override_pm You will have to drop this from devicetree.cb now:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
https://review.coreboot.org/c/coreboot/+/44359/12/src/mainboard/google/volte... PS12, Line 48: cfg->gpio_pm[i] = 0 memset to 0?