[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update s0ix cstate table

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55734 )

Change subject: soc/intel/alderlake: Update s0ix cstate table
......................................................................

soc/intel/alderlake: Update s0ix cstate table

Cstate C7 is not supported in ADL, replacing this unsupported state
with C6 in the s0ix cstate table.

BUG=None
TEST=Boot device to OS.
     Print supported CStates and latencies.

Signed-off-by: Bernardo Perez Priego 
Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Sukumar Ghorai 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Sukumar Ghorai: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index 23d2a26..1f49719 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -107,7 +107,7 @@

static int cstate_set_s0ix[] = {
    C_STATE_C1,
-	C_STATE_C7S_LONG_LAT,
+	C_STATE_C6_LONG_LAT,
    C_STATE_C10
 };