[coreboot-gerrit] Change in coreboot[master]: nb/intel/i440bx: DSDT upgrade

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41049 )

Change subject: nb/intel/i440bx: DSDT upgrade
......................................................................

nb/intel/i440bx: DSDT upgrade

- Separate northbridge DSDT memory device into its own ACPI device,
  in its own file, to be placed in the _SB scope.
  The existing file goes to _SB.PCI0.
- Add PMCR register. It'll come in handy for S3 support.
- Add a memory device in ACPI to match ASUS P3B-F vendor DSDT.
  Memory ranges between TOM and 4GB was declared available for MMIO,
  now it is between TOM and (4GB - CONFIG_ROM_SIZE).

Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df
Signed-off-by: Keith Hui 
---
A src/northbridge/intel/i440bx/acpi/i440bx.asl
M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
2 files changed, 66 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/41049/1

diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl
new file mode 100644
index 0000000..ae82625
--- /dev/null
+++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* i440bx Northbridge resources that sits on _SB */
+
+Device (MEM1)
+{
+	Name (_HID, EisaId ("PNP0C01") /* System Board */)  // _HID: Hardware ID
+	Method (_CRS, 0)  // _CRS: Current Resource Settings
+	{
+		Name (BUF1, ResourceTemplate ()
+		{
+		    Memory32Fixed (ReadWrite,
+			0x00000000,         // Address Base
+			0x000A0000,         // Address Length
+			)
+		    Memory32Fixed (ReadOnly,
+			0x000F0000,         // Address Base
+			0x00010000,         // Address Length
+			)
+		/*
+		 * Main memory. Length of this block will be adjusted to TOM1,
+		 * TOM1-4GB is declared in sb_pci0_crs.asl for MMIO.
+		 */
+		    Memory32Fixed (ReadWrite,
+			0x00100000,         // Address Base
+			0x00000000,         // Address Length
+			_Y00)
+			/* Reserved for firmware flash */
+		    Memory32Fixed (ReadOnly,
+			0xFFFC0000,         // Address Base
+			CONFIG_ROM_SIZE,         // Address Length
+			_Y01)
+		})
+		CreateDWordField (BUF1, _Y00._LEN, EMLN)  // _LEN: Length
+		CreateDWordField (BUF1, _Y01._BAS, FLSB)  // _BAS: Base
+
+		/*
+		 * Use ShiftLeft to avoid 64bit constant (for XP).
+		 * This will work even if the OS does 32bit arithmetic, as
+		 * 32bit (0x00000000 - TOM1) will wrap and give the same
+		 * result as 64bit (0x100000000 - TOM1).
+		 */
+
+		/* Top of 4GB */
+		ShiftLeft(0x10000000, 4, Local0)
+		FLSB = Local0 - CONFIG_ROM_SIZE;
+		EMLN = _SB.PCI0.NB.TOM1 - 0x100000;
+		Return (BUF1) /* _SB_.MEM1._CRS.BUF1 */
+	}
+}
diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
index 856b3e8..476be30 100644
--- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
+++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
@@ -1,22 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */

-/* i440bx Northbridge */
+/* i440bx Northbridge resources that sits on _SB.PCI0 */
 Device (NB)
 {
    Name(_ADR, 0x00000000)
    OperationRegion(PCIC, PCI_Config, 0x00, 0x100)
-}
-
-Field (NB.PCIC, AnyAcc, NoLock, Preserve)
-{
-	Offset (0x67),	// DRB7
-	DRB7,	8,
-}
-
-Method(TOM1, 0) {
-	/* Multiply by 8MB to get TOM */
-	Return(ShiftLeft(DRB7, 23))
+	Field (PCIC, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x67),	// DRB7
+		DRB7,	8,
+		Offset (0x7A),	// PMCR
+		PMCR,	8
+	}
+	Method(TOM1, 0) {
+		/* Multiply by 8MB to get TOM */
+		Return(ShiftLeft(DRB7, 23))
+	}
 }

Method(_CRS, 0) {
@@ -61,10 +61,10 @@
     * 32bit (0x00000000 - TOM1) will wrap and give the same
     * result as 64bit (0x100000000 - TOM1).
     */
-	Store(TOM1, MM1B)
+	MM1B = _SB.PCI0.NB.TOM1
    ShiftLeft(0x10000000, 4, Local0)
-	Subtract(Local0, TOM1, Local0)
-	Store(Local0, MM1L)
+	Local0 -= CONFIG_ROM_SIZE
+	MM1L = Local0 - MM1B

Return(TMP)
 }