Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21224
Change subject: soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculation ......................................................................
soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculation
This patch ensures skylake device using FSP1.1 can use HW based DRAM top calculation which was broken due to skylake fsp1.1 not honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size. This WA is not needed for FSP2.0 implementation due to PrmrrSize UPD is available and considering into hw based dram top calculation.
BRANCH=none BUG=b:63974384 TEST=Build and boot lars which is using skylake 1.1 fsp.
Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/memmap.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/21224/1
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index d5d3724..5014edc 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -178,8 +178,11 @@
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); config = dev->chip_info; +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + prmrr_size = 1*MiB; +#else prmrr_size = config->PrmrrSize; - +#endif if (prmrr_size > 0) { /* * PRMRR Sizes that are > 1MB and < 32MB are