[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail,braswell: Sync PCI memory region in ASL

[Angel Pons (Code Review)]

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50192 )

Change subject: soc/intel/baytrail,braswell: Sync PCI memory region in ASL
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Patch Set 1: Code-Review+2