Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44712 )
Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ......................................................................
Patch Set 46:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 3844: while
i use wait_ms, timeout: 10 seconds.
Ack
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... PS46, Line 3846: SPCMDRESP_MRR_RESPONSE Align with &ch[chn]
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/41/src/soc/mediatek/mt8192/dr... PS41, Line 17: static void get_dram_info_after_cal(struct ddr_cali *cali)
Actually, get dram info contains vendor id, density and so on. […]
Ack
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44712/46/src/soc/mediatek/mt8192/dr... PS46, Line 57: 0x%#x %#x