Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50334 )
Change subject: [UNTESTED] soc/amd/cezanne/pcie_gpp: scan internal PCI buses ......................................................................
[UNTESTED] soc/amd/cezanne/pcie_gpp: scan internal PCI buses
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571 --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/pcie_gpp.c 2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/50334/1
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 9422a4d..45e98a5 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -28,6 +28,7 @@ ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c +ramstage-y += pcie_gpp.c ramstage-y += reset.c ramstage-y += uart.c
diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c new file mode 100644 index 0000000..6cb7656 --- /dev/null +++ b/src/soc/amd/cezanne/pcie_gpp.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations internal_pcie_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, + 0 +}; + +static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { + .ops = &internal_pcie_gpp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; \ No newline at end of file