Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33040
Change subject: sb/intel/bd82x6x: Use common final SPI OPs setup ......................................................................
sb/intel/bd82x6x: Use common final SPI OPs setup
This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi.
Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/lpc.c 3 files changed, 24 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33040/1
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59df..1ad58b8 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -56,7 +56,14 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" - register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }" + register "spi.ops" = "{ {0x01, WRITE_NO_ADDR }, + {0x02, WRITE_WITH_ADDR }, + {0x03, READ_WITH_ADDR }, + {0x05, READ_NO_ADDR }, + {0x20, WRITE_WITH_ADDR }, + {0x9f, READ_NO_ADDR }, + {0xad, WRITE_NO_ADDR }, + {0x04, WRITE_NO_ADDR } }" device pci 16.0 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 29f6881..d04cbec 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
+#include <southbridge/intel/common/spi.h> #include <stdint.h>
struct southbridge_intel_bd82x6x_config { @@ -97,14 +98,7 @@
uint32_t spi_uvscc; uint32_t spi_lvscc; - struct { - uint8_t opprefixes[2]; - struct { - uint8_t needs_address; - uint8_t is_write; - uint8_t op; - } ops[8]; - } spi; + struct intel_spi_config spi; };
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7737501..9615698 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -38,6 +38,7 @@ #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/common/spi.h>
#define NMI_OFF 0
@@ -875,34 +876,6 @@
static void lpc_final(struct device *dev) { - u16 spi_opprefix = SPI_OPPREFIX; - u16 spi_optype = SPI_OPTYPE; - u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }; - - /* Configure SPI opcode menu; devicetree may override defaults. */ - const config_t *const config = dev->chip_info; - if (config && config->spi.ops[0].op) { - unsigned int i; - - spi_opprefix = 0; - spi_optype = 0; - spi_opmenu[0] = 0; - spi_opmenu[1] = 0; - for (i = 0; i < sizeof(spi_opprefix); ++i) - spi_opprefix |= config->spi.opprefixes[i] << i * 8; - for (i = 0; i < sizeof(spi_opmenu); ++i) { - spi_optype |= - config->spi.ops[i].is_write << 2 * i | - config->spi.ops[i].needs_address << (2 * i + 1); - spi_opmenu[i / 4] |= - config->spi.ops[i].op << (i % 4) * 8; - } - } - RCBA16(0x3894) = spi_opprefix; - RCBA16(0x3896) = spi_optype; - RCBA32(0x3898) = spi_opmenu[0]; - RCBA32(0x389c) = spi_opmenu[1]; - /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || @@ -918,6 +891,19 @@ } }
+void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + /* Devicetree may override defaults. */ + const config_t *const config = dev->chip_info; + + if (config) + return; + + if (config->spi.ops[0].op != 0) + memcpy(spi_config, &config->spi, sizeof(config->spi)); +} + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, };