Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55987 )
Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads ......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/55987/comment/07037269_52c79c94 PS2, Line 83: MPB_MAX_SIZE Reading rest of the code again, could it be the case that there are multiple microcode files added to CBFS within "cpu_microcode_blob.bin"? That seems like a possibility looking at how `amd_update_mirocode()` loops over the provided entries.
Also, picasso seems to have add multiple microcode files. So, this is not really going to work with MBP_MAX_SIZE:
``` find -name UcodePatch* ./amd_blobs/cezanne/PSP/UcodePatch_CZN_A0.bin ./amd_blobs/picasso/PSP/UcodePatch_PCO_B0.bin ./amd_blobs/picasso/PSP/UcodePatch_RV2_A0.bin ./amd_blobs/picasso/PSP/UcodePatch_PCO_B1.bin ```
What we will have to probably do is:
1. cbfs_map entire `cpu_microcode_blob.bin` 2. Loop over the entries to find the matching entry for the processor rev_id 3. Make a copy of the matching microcode into local buffer.
This will require refactoring `amd_update_microcode()` to move the matching of the rev_id to this function.