[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: Drop use of SPD cache for puff-based variants

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47899 )

Change subject: mb/google/hatch: Drop use of SPD cache for puff-based variants
......................................................................

mb/google/hatch: Drop use of SPD cache for puff-based variants

Commit 74109923 [mb/google/puff: add a region to cache SPD data]
implemented a mechanism to cache SODIMM SPD data in a FMAP region,
but it's actually slower than simply letting FSP (vs coreboot)
read the SPD data via smbus, so drop it.

This has the side effect of removing the requirement for a
RW_SPD_CACHE FMAP region, without which these boards would not
boot at all - allowing the default FMAP to be used for non-ChromeOS
builds.

Test: build/boot WYVERN variant, check boot times via cbmem:
w/SPD caching: ~722 ms
w/FSP reading: ~627 ms

Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/hatch/romstage_spd_smbus.c
1 file changed, 5 insertions(+), 56 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47899/1

diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c
index e697379..1db9c54 100644
--- a/src/mainboard/google/hatch/romstage_spd_smbus.c
+++ b/src/mainboard/google/hatch/romstage_spd_smbus.c
@@ -1,72 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <baseboard/variants.h>
-#include <console/console.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
-#include <spd_bin.h>
-#include <spd_cache.h>

void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
    struct cnl_mb_cfg memcfg;
    variant_memory_params(&memcfg);

-	/* Read spd block to get memory config */
-	struct spd_block blk = {
-		.addr_map = { 0x50, 0x52, },
-	};
-
-	uint8_t *spd_cache;
-	size_t spd_cache_sz;
-	bool need_update_cache = false;
-	bool dimm_changed = true;
-
-	/* load spd cache from RW_SPD_CACHE */
-	if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) {
-		if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) {
-			printk(BIOS_WARNING, "Invalid SPD cache\n");
-		} else {
-			dimm_changed = check_if_dimm_changed(spd_cache, &blk);
-			if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) {
-				/* Set mrc_cache as invalid */
-				printk(BIOS_INFO, "Set mrc_cache as invalid\n");
-				memupd->FspmArchUpd.NvsBufferPtr = NULL;
-			}
-		}
-		need_update_cache = true;
-	}
-
-	if (!dimm_changed) {
-		spd_fill_from_cache(spd_cache, &blk);
-	} else {
-		/* Access memory info through SMBUS. */
-		get_spd_smbus(&blk);
-
-		if (need_update_cache && update_spd_cache(&blk) == CB_ERR)
-			printk(BIOS_WARNING, "update SPD cache failed\n");
-	}
-
-	if (blk.spd_array[0] == NULL) {
-		memcfg.spd[0].read_type = NOT_EXISTING;
-	} else {
-		memcfg.spd[0].read_type = READ_SPD_MEMPTR;
-		memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len;
-		memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0];
-	}
-
+	/* DDR4 SODIMMs located at CH0D0, CH1D0 */
+	memcfg.spd[0].read_type = READ_SMBUS;
+	memcfg.spd[0].spd_spec.spd_smbus_address = 0xa0;
    memcfg.spd[1].read_type = NOT_EXISTING;
-
-	if (blk.spd_array[1] == NULL) {
-		memcfg.spd[2].read_type = NOT_EXISTING;
-	} else {
-		memcfg.spd[2].read_type = READ_SPD_MEMPTR;
-		memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len;
-		memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1];
-	}
-
+	memcfg.spd[2].read_type = READ_SMBUS;
+	memcfg.spd[2].spd_spec.spd_smbus_address = 0xa4;
    memcfg.spd[3].read_type = NOT_EXISTING;
-	dump_spd_info(&blk);

/* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */
    memcfg.vref_ca_config = 2;