Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang.
Hello Chen, Gang C, Ziang Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/81443?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ......................................................................
soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
Add a new proximity type to represent the sub-NUMA cluster.
Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu shuo.liu@intel.com Signed-off-by: Ziang Wang ziang.wang@intel.com Signed-off-by: Gang Chen gang.c.chen@intel.com --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 5 files changed, 26 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81443/1
diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index b00eb88..58a31da 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -17,6 +17,7 @@ * Generic Initiator domain is a CXL memory device. */ PD_TYPE_GENERIC_INITIATOR, + PD_TYPE_CLUSTER, PD_TYPE_MAX };
@@ -38,6 +39,7 @@ * sockets, so we need a bitmap. */ uint8_t socket_bitmap; + uint8_t cluster_bitmap; /* Relative distances (memory latency) from all domains */ uint8_t *distances; /* @@ -68,4 +70,6 @@ uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem); uint32_t device_to_pd(const struct device *dev);
+uint8_t soc_get_cluster_count(void); + #endif /* NUMA_H */ diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 8340f4d..e9ffa18 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -19,6 +19,7 @@ printk(BIOS_DEBUG, "\tproximity domain %d:\n", i); printk(BIOS_DEBUG, "\t\ttype:%d\n", pds.pds[i].pd_type); printk(BIOS_DEBUG, "\t\tsocket_bitmap:0x%x\n", pds.pds[i].socket_bitmap); + printk(BIOS_DEBUG, "\t\tcluster_bitmap:0x%x\n", pds.pds[i].cluster_bitmap); printk(BIOS_DEBUG, "\t\tdevice:%s\n", pds.pds[i].dev ? dev_path(pds.pds[i].dev) : ""); printk(BIOS_DEBUG, "\t\tbase(64MB):0x%x\n", pds.pds[i].base); printk(BIOS_DEBUG, "\t\tsize(64MB):0x%x\n", pds.pds[i].size); @@ -29,6 +30,7 @@ { uint8_t num_sockets = soc_get_num_cpus(); uint8_t num_cxlnodes = get_cxl_node_count(); + uint8_t num_clusters = soc_get_cluster_count(); const IIO_UDS *hob = get_iio_uds();
/* @@ -42,7 +44,7 @@ * HDM has one and only one CXL node info entry. Each CXL node info entry * represents a generic initiator proximity domain. */ - pds.num_pds = num_cxlnodes + num_sockets; + pds.num_pds = num_cxlnodes + num_sockets + num_sockets * num_clusters; pds.pds = xmalloc(sizeof(struct proximity_domain) * pds.num_pds); if (!pds.pds) die("%s %d out of memory.", __FILE__, __LINE__); @@ -60,6 +62,16 @@ if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); i++; + /* Fill in cluster domains */ + for (uint8_t cluster = 0; cluster < num_clusters; cluster++) { + pds.pds[i].pd_type = PD_TYPE_CLUSTER; + pds.pds[i].socket_bitmap = 1 << hob->PlatformData.IIO_resource[socket].SocketID; + pds.pds[i].cluster_bitmap = 1 << cluster; + pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); + if (!pds.pds[i].distances) + die("%s %d out of memory.", __FILE__, __LINE__); + i++; + } }
/* If there are no CXL nodes, we are done */ @@ -97,7 +109,7 @@ uint32_t size = 0;
for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; size += pds.pds[i].size; } @@ -166,3 +178,8 @@ } } } + +__weak uint8_t soc_get_cluster_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 7b934ba..30432b5 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -177,7 +177,7 @@ uint32_t ep_bus; uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; ep_bus = PCI_BDF(pds.pds[i].dev) >> 20; if (ep_bus == ecrc_bus + 1) diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 41b256c..7a3308d 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -93,7 +93,7 @@ bool is_iio_cxl_stack_res(const STACK_RES *res) { for (uint8_t i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue;
uint32_t bus = PCI_BDF(pds.pds[i].dev) >> 20; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 306aaf3..b2db4ed94 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -284,7 +284,7 @@ /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue;
if (CONFIG(OCP_VPD)) {